1. Field of the Invention
The present invention relates to a method for producing a Schottky junction field effect transistor (i. e., metal semiconductor field effect transistor, herebelow referred to as MESFET) having a recess gate structure. The method is adopted to semiconductor processes for a high electron mobility transistor (herebelow referred to as HEMT) or the like that is operated at high frequency.
2. Related Arts
A MESFET generally includes source and drain electrodes making an ohmic contact with a semiconductor layer and a gate electrode disposed between the source and drain electrodes and making a Schottky contact with the semiconductor layer. A drain current in the MESFET is controlled by a field effect of the gate electrode. The MESFET can be used as a high frequency semiconductor element by adopting material such as GaAs having a high mobility for the semiconductor layer. Further, recently, a HEMT capable of being operated at higher frequency has been studied and developed. The HEMT includes a semiconductor hetero junction to have a doped layer for producing carriers therein and a channel layer separated from the doped layer for transferring the carriers therethrough, realizing high frequency operation.
In these field effect transistors (FET), a recess gate structure is widely employed as a structure of the gate electrode making a Schottky contact. When this kind of FET having the recess gate structure is manufactured, as shown in FIG. 1, an ohmic contact layer 70a having a high doping concentration is formed in a surface region of a semiconductor substrate 70, and source and drain electrodes 71 and 72 are disposed on the ohmic contact layer 70a. Further, as shown in FIG. 2, a photo-resist layer 73 is disposed on the substrate 70 to have a specific pattern. Then, a part of the ohmic contact layer 70a where a gate electrode 76 (see FIG. 5) is to be formed is removed by etching using the resist layer 73 as a mask. Accordingly, a recess 74 is formed as shown in FIG. 3. Successively, as shown in FIG. 4, an electrode member 75 is deposited on the photo-resist layer 73 and in the recess 74. Then, as shown in FIG. 5, the gate electrode 76 is formed by performing a metal lift-off process with respect to the electrode member 75. Finally, as shown in FIG. 6, an insulating layer 77, a source wiring member 78, and a drain wiring member 79 are formed.
Advantageous of the above-mentioned recess gate structure are that contact resistances of the gate, source, and drain electrodes, 76, 71, and 72 can be reduced and that intervals between both ends of the gate electrode 76 and the ohmic contact layer 70a can be narrowed by self-alignment. Consequently, a source resistance and variations in the source resistance can be reduced.
However, in the above-mentioned method, the gate electrode 76 is formed by using the resist layer 73, and the source and drain electrodes 71 and 72 are formed by using another resist layer. Therefore, this method is liable to produce alignment deviation of the gate electrode 76 with respect to the source and drain electrodes 71 and 72. That is, it is difficult to secure specific intervals L10 and L20 (see FIG. 6) between the gate and source electrodes 76 and 71 and between the gate and drain electrodes 76 and 72.
To solve the problem, JP-A-2-285644 discloses a technique for arranging a gate electrode in a recess gate structure with a high accuracy. Specifically, when a T-type Schottky gate electrode is arranged with respect to source and drain electrodes, three types of insulating layers are used. More specifically, an L-type and a reverse L-type insulating layers are formed by utilizing side walls of another layer. Then, the gate electrode is positioned with respect to the source and drain electrodes by using the insulating layers to provide relatively small intervals with respect to the source and drain electrodes. However, this technique needs formation processes for the three types of insulating layers and etching processes for the layers. Additionally, it is necessary to perform complicated processes such as an ion milling process for the gate electrode. As a result, manufacturing cost is increased.
On the other hand, recently, various semiconductor materials have been studied to improve operation frequency of an FET. For example, a HEMT structure having a hetero junction of an InAlAs doped layer and an InGaAs channel layer is proposed to achieve a significantly high mobility. In this structure, however, a gate electrode needs to be formed on the InAlAs layer. It is difficult for the gate electrode to exhibit sufficient Schottky characteristics on the InAlAs layer. In addition, when the HEMT structure includes the above-mentioned recess gate structure, it is difficult to obtain a sufficient drain withstand voltage.
As a technique to solve this problem, a double recess structure is proposed in, for example, "DOUBLE-RECESS LATTICE-MATCHED MEMT", an autumn conference of the electronic information communication society, 1991, pp. 2-312, by Hisao Kawasaki et al. A method for producing an FET having the double recess structure is as follows. Firstly, as shown in FIG. 7, source and drain electrodes 81 and 82 are disposed on a substrate 80. Then, as shown in FIG. 8, a first recess 84 is formed in the substrate 80 between the source and drain electrodes 81 and 82 by an etching process using a first resist layer 83 as a mask. After forming the first recess 84, the first resist layer 83 is removed. Then, as shown in FIG. 9, a second resist layer 85 is formed on a bottom face of the recess 84 as well as on the source and drain electrodes 81 and 82, and a second recess 86 is formed by an etching process using the second resist layer 85 as a mask as shown in FIG. 10. Further, as shown in FIG. 11, an electrode member 87 is deposited on a bottom face of the second recess 86 and on the resist layer 85. Then, in a state where only a gate electrode 88 remains in the recess 86 as shown in FIG. 12, an insulating layer 89, a source wiring member 90, and a drain wiring member 91 are formed as shown in FIG. 13.
Thus, in the method for forming the double recess structure, because the mask 85 for forming the gate electrode 88 is different from the mask 83 for forming the first recess 84, a width of the first recess 84 can be lengthened regardless of a width of the gate electrode 88. As a result, a drain withstand voltage of the FET can be improved.
However, this method has the following problem. That is, in the single recess structure shown in FIG. 6, intervals between the gate electrode 76 and the ohmic contact layer 70a can be set by self-alignment. As opposed to this, in the double recess structure shown in FIG. 13, intervals L12 and L13 between the gate electrode 88 and an ohmic contact layer 80a are liable to have variations due to a deviation in mask alignment. The variations in intervals L12 and L13 cause variations in source resistance, variations in drain withstand voltage and the like. The variations in the source resistance further cause variations in high frequency parameter. As a result, various problems occur in a high frequency circuit using the FET.
In this way, although the double recess structure is effective for HEMT and MESFET to improve the drain withstand voltages thereof, the variations in the intervals L12 and L13 between the gate electrode 88 and the ohmic contact layer 80a in the double recess structure cause the above-mentioned problems. The variations in the intervals L12 and L13 are produced by the deviation in the mask alignment between the first recess 84 and the gate electrode 88. Therefore, it is necessary that alignment of the gate electrode 88 is precisely performed with respect to the first recess pattern to decrease the variations in the intervals L12 and L13. However, a depth of the first recess 84 shown in FIG. 8 is too shallow to be detected through the resist layer 85 shown in FIG. 9. Because of this, conventionally, the first recess 84 is aligned with respect to a reference pattern as shown in FIG. 8, and then, the gate electrode 88 is aligned with respect to another reference pattern as shown in FIG. 9.
Consequently, an amount of the deviation in the mask alignment between the first recess 84 and the gate electrode 88 is the sum of amounts of deviations in mask alignment of the first recess 84 with respect to the reference pattern and of the gate electrode 88 with respect to the another reference pattern. As a result, the amount of the deviation in the mask alignment between the first recess 84 and the gate electrode 88 becomes large.